Hardware Verification Engineer [5, Shanghai/Chengdu]

Responsibilities:
The candidate will be responsible for building up verification environment 
and
completing verification of design and algorithm at both chip and unit 
levels.
The candidate may also be responsible for logic design and implementation 
in 
low power graphic and multi-media chip/core, silicon bring-up, etc.

Requirements:

1.     　Master degree or above;
2.     　Good in logic design, simulation, synthesis and test;
3.     　Experience with C and C++ and script language like PERL/PYTHON/TCL, 
etc;
4.     　Familiar with all aspects of the frontend ASIC design flow 
including RTL de
sign, verification, synthesis, and timing analysis, DFT, etc;
5.     　Experience with high-level verification languages such as System 
Verilog, V
era, System C or Specman e language is a plus;
6.     　Experience in graphic, video, and multi-media chip design is a big 
plus;
7.     　Self-motivated and good team player;
8.     　Good written and spoken English;
9.     　Good communication skills and able to work both independently and 
in a team